// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  gicr_dfx_regs_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/05/11 14:50:32 Create file
// ******************************************************************************

#ifndef __GICR_DFX_REGS_REG_OFFSET_FIELD_H__
#define __GICR_DFX_REGS_REG_OFFSET_FIELD_H__

#define GICR_DFX_REGS_GICR_AXUSER_FP_LEN           1
#define GICR_DFX_REGS_GICR_AXUSER_FP_OFFSET        23
#define GICR_DFX_REGS_GICR_AXUSER_TYPE_LEN         2
#define GICR_DFX_REGS_GICR_AXUSER_TYPE_OFFSET      21
#define GICR_DFX_REGS_GICR_AXUSER_CLEANINV_LEN     1
#define GICR_DFX_REGS_GICR_AXUSER_CLEANINV_OFFSET  20
#define GICR_DFX_REGS_GICR_AXUSER_FNA_LEN          1
#define GICR_DFX_REGS_GICR_AXUSER_FNA_OFFSET       19
#define GICR_DFX_REGS_GICR_AXUSER_FA_LEN           1
#define GICR_DFX_REGS_GICR_AXUSER_FA_OFFSET        18
#define GICR_DFX_REGS_GICR_AXUSER_SNAPATTR_LEN     2
#define GICR_DFX_REGS_GICR_AXUSER_SNAPATTR_OFFSET  16
#define GICR_DFX_REGS_GICR_AXUSER_REQUESTID_LEN    16
#define GICR_DFX_REGS_GICR_AXUSER_REQUESTID_OFFSET 0

#define GICR_DFX_REGS_VERSION_ID_LEN    32
#define GICR_DFX_REGS_VERSION_ID_OFFSET 0

#define GICR_DFX_REGS_DIE_EN_CROSS_LEN    16
#define GICR_DFX_REGS_DIE_EN_CROSS_OFFSET 0

#define GICR_DFX_REGS_DIE_EN_CROSS_SPI_12N_LEN    16
#define GICR_DFX_REGS_DIE_EN_CROSS_SPI_12N_OFFSET 0

#define GICR_DFX_REGS_DIE_EN_CROSS_SPI_N2N_LEN    16
#define GICR_DFX_REGS_DIE_EN_CROSS_SPI_N2N_OFFSET 0

#define GICR_DFX_REGS_DIE_EN_CROSS_SGI_N2N_LEN    16
#define GICR_DFX_REGS_DIE_EN_CROSS_SGI_N2N_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_0_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_0_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_1_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_1_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_2_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_2_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_3_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_3_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_4_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_4_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_5_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_5_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_6_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_6_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_7_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_7_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_8_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_8_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_9_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_9_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_10_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_10_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_11_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_11_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_12_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_12_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_13_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_13_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_14_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_14_OFFSET 0

#define GICR_DFX_REGS_CROSSDIE_BASEADDR_15_LEN    32
#define GICR_DFX_REGS_CROSSDIE_BASEADDR_15_OFFSET 0

#define GICR_DFX_REGS_DFX_CPU_SEL_LEN         5
#define GICR_DFX_REGS_DFX_CPU_SEL_OFFSET      24
#define GICR_DFX_REGS_DFX_MON_LPI_CMD_LEN     4
#define GICR_DFX_REGS_DFX_MON_LPI_CMD_OFFSET  20
#define GICR_DFX_REGS_DFX_INT_TYPE_SEL_LEN    1
#define GICR_DFX_REGS_DFX_INT_TYPE_SEL_OFFSET 16
#define GICR_DFX_REGS_DFX_MON_LPI_ID_LEN      16
#define GICR_DFX_REGS_DFX_MON_LPI_ID_OFFSET   0

#define GICR_DFX_REGS_SNAP_EN_LEN       1
#define GICR_DFX_REGS_SNAP_EN_OFFSET    1
#define GICR_DFX_REGS_CNT_CLR_CE_LEN    1
#define GICR_DFX_REGS_CNT_CLR_CE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_0_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_0_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_1_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_1_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_2_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_2_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_3_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_3_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_4_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_4_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_5_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_5_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_6_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_6_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_7_LEN    24
#define GICR_DFX_REGS_DFX_LPI_CACHE_DATA_7_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_ADDR_LEN     4
#define GICR_DFX_REGS_DFX_LPI_CACHE_ADDR_OFFSET  5
#define GICR_DFX_REGS_DFX_LPI_UP_MARKED_LEN      1
#define GICR_DFX_REGS_DFX_LPI_UP_MARKED_OFFSET   4
#define GICR_DFX_REGS_DFX_LPI_UP_REQ_LEN         1
#define GICR_DFX_REGS_DFX_LPI_UP_REQ_OFFSET      3
#define GICR_DFX_REGS_DFX_LPI_CACHE_FULL_LEN     1
#define GICR_DFX_REGS_DFX_LPI_CACHE_FULL_OFFSET  2
#define GICR_DFX_REGS_DFX_LPI_CACHE_ALF_LEN      1
#define GICR_DFX_REGS_DFX_LPI_CACHE_ALF_OFFSET   1
#define GICR_DFX_REGS_DFX_LPI_CACHE_EMPTY_LEN    1
#define GICR_DFX_REGS_DFX_LPI_CACHE_EMPTY_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CACHE_RESERVE_LEN    8
#define GICR_DFX_REGS_DFX_LPI_CACHE_RESERVE_OFFSET 24
#define GICR_DFX_REGS_DFX_LPI_CACHE_VLD_LEN        8
#define GICR_DFX_REGS_DFX_LPI_CACHE_VLD_OFFSET     16
#define GICR_DFX_REGS_DFX_LPI_CACHE_MRK_LEN        8
#define GICR_DFX_REGS_DFX_LPI_CACHE_MRK_OFFSET     8
#define GICR_DFX_REGS_DFX_LPI_CACHE_DTY_LEN        8
#define GICR_DFX_REGS_DFX_LPI_CACHE_DTY_OFFSET     0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_0_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_0_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_1_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_1_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_2_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_2_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_3_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_3_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_4_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_4_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_5_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_5_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_6_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_6_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_7_LEN    24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DATA_7_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_ADDR_LEN     4
#define GICR_DFX_REGS_DFX_VLPI_CACHE_ADDR_OFFSET  5
#define GICR_DFX_REGS_DFX_VLPI_UP_MARKED_LEN      1
#define GICR_DFX_REGS_DFX_VLPI_UP_MARKED_OFFSET   4
#define GICR_DFX_REGS_DFX_VLPI_UP_REQ_LEN         1
#define GICR_DFX_REGS_DFX_VLPI_UP_REQ_OFFSET      3
#define GICR_DFX_REGS_DFX_VLPI_CACHE_FULL_LEN     1
#define GICR_DFX_REGS_DFX_VLPI_CACHE_FULL_OFFSET  2
#define GICR_DFX_REGS_DFX_VLPI_CACHE_ALF_LEN      1
#define GICR_DFX_REGS_DFX_VLPI_CACHE_ALF_OFFSET   1
#define GICR_DFX_REGS_DFX_VLPI_CACHE_EMPTY_LEN    1
#define GICR_DFX_REGS_DFX_VLPI_CACHE_EMPTY_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CACHE_RESERVE_LEN    8
#define GICR_DFX_REGS_DFX_VLPI_CACHE_RESERVE_OFFSET 24
#define GICR_DFX_REGS_DFX_VLPI_CACHE_VLD_LEN        8
#define GICR_DFX_REGS_DFX_VLPI_CACHE_VLD_OFFSET     16
#define GICR_DFX_REGS_DFX_VLPI_CACHE_MRK_LEN        8
#define GICR_DFX_REGS_DFX_VLPI_CACHE_MRK_OFFSET     8
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DTY_LEN        8
#define GICR_DFX_REGS_DFX_VLPI_CACHE_DTY_OFFSET     0

#define GICR_DFX_REGS_DFX_CROSSDIE_SET_REQ_SPI_LEN    1
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_REQ_SPI_OFFSET 4
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_REQ_SGI_LEN    1
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_REQ_SGI_OFFSET 3
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_RDY_SPI_LEN    1
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_RDY_SPI_OFFSET 2
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_RDY_SGI_LEN    1
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_RDY_SGI_OFFSET 1
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_RDY_LEN        1
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_RDY_OFFSET     0

#define GICR_DFX_REGS_DFX_CROSSDIE_SET_CNT_SPI_LEN    16
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_CNT_SPI_OFFSET 16
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_CNT_SGI_LEN    16
#define GICR_DFX_REGS_DFX_CROSSDIE_SET_CNT_SGI_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_RESREVE0_LEN                     11
#define GICR_DFX_REGS_DFX_LPI_RESREVE0_OFFSET                  21
#define GICR_DFX_REGS_DFX_LPI_CMD_IDLE_LEN                     1
#define GICR_DFX_REGS_DFX_LPI_CMD_IDLE_OFFSET                  20
#define GICR_DFX_REGS_DFX_LPI_CMD_CTRL_CS_LEN                  3
#define GICR_DFX_REGS_DFX_LPI_CMD_CTRL_CS_OFFSET               17
#define GICR_DFX_REGS_DFX_LPI_IDLE_LEN                         1
#define GICR_DFX_REGS_DFX_LPI_IDLE_OFFSET                      16
#define GICR_DFX_REGS_DFX_LPI_CMD_CS_LEN                       5
#define GICR_DFX_REGS_DFX_LPI_CMD_CS_OFFSET                    11
#define GICR_DFX_REGS_DFX_LPI_PMR_VLD_LEN                      1
#define GICR_DFX_REGS_DFX_LPI_PMR_VLD_OFFSET                   10
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_CMD_LEN                  4
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_CMD_OFFSET               6
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_RTYB_FULL_LEN            1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_RTYB_FULL_OFFSET         5
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_RTYB_EMPTY_LEN           1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_RTYB_EMPTY_OFFSET        4
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOV_WAITING_LEN          1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOV_WAITING_OFFSET       3
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_INVALL_RUNNING_LEN       1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_INVALL_RUNNING_OFFSET    2
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVCACHE_RUNNING_LEN     1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVCACHE_RUNNING_OFFSET  1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVMEMORY_RUNNING_LEN    1
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVMEMORY_RUNNING_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_PTSRCH_IDLE_LEN             1
#define GICR_DFX_REGS_DFX_LPI_PTSRCH_IDLE_OFFSET          31
#define GICR_DFX_REGS_DFX_LPI_PTSRCH_CS_LEN               3
#define GICR_DFX_REGS_DFX_LPI_PTSRCH_CS_OFFSET            28
#define GICR_DFX_REGS_DFX_LPI_ADD_IDLE_LEN                1
#define GICR_DFX_REGS_DFX_LPI_ADD_IDLE_OFFSET             27
#define GICR_DFX_REGS_DFX_LPI_ADD_CS_LEN                  4
#define GICR_DFX_REGS_DFX_LPI_ADD_CS_OFFSET               23
#define GICR_DFX_REGS_DFX_LPI_ADD_CPT_NFOUND_ERROR_LEN    1
#define GICR_DFX_REGS_DFX_LPI_ADD_CPT_NFOUND_ERROR_OFFSET 22
#define GICR_DFX_REGS_DFX_LPI_ADD_PT_NFOUND_ERROR_LEN     1
#define GICR_DFX_REGS_DFX_LPI_ADD_PT_NFOUND_ERROR_OFFSET  21
#define GICR_DFX_REGS_DFX_LPI_CPTPD_INMEMORY_CNT_LEN      7
#define GICR_DFX_REGS_DFX_LPI_CPTPD_INMEMORY_CNT_OFFSET   14
#define GICR_DFX_REGS_DFX_LPI_PTPD_INCPT_CNT_LEN          10
#define GICR_DFX_REGS_DFX_LPI_PTPD_INCPT_CNT_OFFSET       4
#define GICR_DFX_REGS_DFX_LPI_EXIST_PENDING_VLD_LEN       1
#define GICR_DFX_REGS_DFX_LPI_EXIST_PENDING_VLD_OFFSET    3
#define GICR_DFX_REGS_DFX_LPI_EXIST_PD_NOTFOUND_LEN       1
#define GICR_DFX_REGS_DFX_LPI_EXIST_PD_NOTFOUND_OFFSET    2
#define GICR_DFX_REGS_DFX_LPI_EXIST_PD_AFTER_ADD_LEN      1
#define GICR_DFX_REGS_DFX_LPI_EXIST_PD_AFTER_ADD_OFFSET   1
#define GICR_DFX_REGS_DFX_LPI_EXIST_PD_VCPU_CHANGE_LEN    1
#define GICR_DFX_REGS_DFX_LPI_EXIST_PD_VCPU_CHANGE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_RESREVE2_LEN      13
#define GICR_DFX_REGS_DFX_LPI_RESREVE2_OFFSET   19
#define GICR_DFX_REGS_DFX_LPI_CMD_TYPE_LEN      3
#define GICR_DFX_REGS_DFX_LPI_CMD_TYPE_OFFSET   16
#define GICR_DFX_REGS_DFX_LPI_CMD_ID_ACP_LEN    16
#define GICR_DFX_REGS_DFX_LPI_CMD_ID_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_RESREVE3_LEN      4
#define GICR_DFX_REGS_DFX_LPI_RESREVE3_OFFSET   28
#define GICR_DFX_REGS_DFX_LPI_CMD_TA_ACP_LEN    28
#define GICR_DFX_REGS_DFX_LPI_CMD_TA_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_ACP_LEN    32
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_INVALL_DONE_LEN    32
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_INVALL_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_SET_SAMEID_LEN    32
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_SET_SAMEID_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVMEMORY_DONE_LEN    32
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVMEMORY_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVALL_DONE_LEN    32
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOVALL_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_SINGLE_DONE_LEN    32
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_SINGLE_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_ADD_ENABLE_LEN    32
#define GICR_DFX_REGS_DFX_LPI_ADD_ENABLE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_ADD_SEARCH_DONE_LEN    32
#define GICR_DFX_REGS_DFX_LPI_ADD_SEARCH_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_ADD_MOVBRESP_ACK_LEN    32
#define GICR_DFX_REGS_DFX_LPI_ADD_MOVBRESP_ACK_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_RESREVE0_LEN                     11
#define GICR_DFX_REGS_DFX_VLPI_RESREVE0_OFFSET                  21
#define GICR_DFX_REGS_DFX_VLPI_CMD_IDLE_LEN                     1
#define GICR_DFX_REGS_DFX_VLPI_CMD_IDLE_OFFSET                  20
#define GICR_DFX_REGS_DFX_VLPI_CMD_CTRL_CS_LEN                  3
#define GICR_DFX_REGS_DFX_VLPI_CMD_CTRL_CS_OFFSET               17
#define GICR_DFX_REGS_DFX_VLPI_IDLE_LEN                         1
#define GICR_DFX_REGS_DFX_VLPI_IDLE_OFFSET                      16
#define GICR_DFX_REGS_DFX_VLPI_CMD_CS_LEN                       5
#define GICR_DFX_REGS_DFX_VLPI_CMD_CS_OFFSET                    11
#define GICR_DFX_REGS_DFX_VLPI_PMR_VLD_LEN                      1
#define GICR_DFX_REGS_DFX_VLPI_PMR_VLD_OFFSET                   10
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_CMD_LEN                  4
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_CMD_OFFSET               6
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_RTYB_FULL_LEN            1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_RTYB_FULL_OFFSET         5
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_RTYB_EMPTY_LEN           1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_RTYB_EMPTY_OFFSET        4
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOV_WAITING_LEN          1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOV_WAITING_OFFSET       3
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_INVALL_RUNNING_LEN       1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_INVALL_RUNNING_OFFSET    2
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOVCACHE_RUNNING_LEN     1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOVCACHE_RUNNING_OFFSET  1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOVMEMORY_RUNNING_LEN    1
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOVMEMORY_RUNNING_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_PTSRCH_IDLE_LEN             1
#define GICR_DFX_REGS_DFX_VLPI_PTSRCH_IDLE_OFFSET          31
#define GICR_DFX_REGS_DFX_VLPI_PTSRCH_CS_LEN               3
#define GICR_DFX_REGS_DFX_VLPI_PTSRCH_CS_OFFSET            28
#define GICR_DFX_REGS_DFX_VLPI_ADD_IDLE_LEN                1
#define GICR_DFX_REGS_DFX_VLPI_ADD_IDLE_OFFSET             27
#define GICR_DFX_REGS_DFX_VLPI_ADD_CS_LEN                  4
#define GICR_DFX_REGS_DFX_VLPI_ADD_CS_OFFSET               23
#define GICR_DFX_REGS_DFX_VLPI_ADD_CPT_NFOUND_ERROR_LEN    1
#define GICR_DFX_REGS_DFX_VLPI_ADD_CPT_NFOUND_ERROR_OFFSET 22
#define GICR_DFX_REGS_DFX_VLPI_ADD_PT_NFOUND_ERROR_LEN     1
#define GICR_DFX_REGS_DFX_VLPI_ADD_PT_NFOUND_ERROR_OFFSET  21
#define GICR_DFX_REGS_DFX_VLPI_CPTPD_INMEMORY_CNT_LEN      7
#define GICR_DFX_REGS_DFX_VLPI_CPTPD_INMEMORY_CNT_OFFSET   14
#define GICR_DFX_REGS_DFX_VLPI_PTPD_INCPT_CNT_LEN          10
#define GICR_DFX_REGS_DFX_VLPI_PTPD_INCPT_CNT_OFFSET       4
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PENDING_VLD_LEN       1
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PENDING_VLD_OFFSET    3
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PD_NOTFOUND_LEN       1
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PD_NOTFOUND_OFFSET    2
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PD_AFTER_ADD_LEN      1
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PD_AFTER_ADD_OFFSET   1
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PD_VCPU_CHANGE_LEN    1
#define GICR_DFX_REGS_DFX_VLPI_EXIST_PD_VCPU_CHANGE_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_RESREVE2_LEN      13
#define GICR_DFX_REGS_DFX_VLPI_RESREVE2_OFFSET   19
#define GICR_DFX_REGS_DFX_VLPI_CMD_TYPE_LEN      3
#define GICR_DFX_REGS_DFX_VLPI_CMD_TYPE_OFFSET   16
#define GICR_DFX_REGS_DFX_VLPI_CMD_ID_ACP_LEN    16
#define GICR_DFX_REGS_DFX_VLPI_CMD_ID_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_RESREVE3_LEN      4
#define GICR_DFX_REGS_DFX_VLPI_RESREVE3_OFFSET   28
#define GICR_DFX_REGS_DFX_VLPI_CMD_TA_ACP_LEN    28
#define GICR_DFX_REGS_DFX_VLPI_CMD_TA_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_RESREVE4_LEN       4
#define GICR_DFX_REGS_DFX_VLPI_RESREVE4_OFFSET    28
#define GICR_DFX_REGS_DFX_VLPI_CMD_VPT_ACP_LEN    28
#define GICR_DFX_REGS_DFX_VLPI_CMD_VPT_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_ACP_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_ACP_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_INVALL_DONE_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_INVALL_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOVALL_DONE_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_MOVALL_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_SINGLE_DONE_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_SINGLE_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_SET_SAMEID_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_CMD_LPI_SET_SAMEID_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_ADD_ENABLE_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_ADD_ENABLE_OFFSET 0

#define GICR_DFX_REGS_DFX_VLPI_ADD_SEARCH_DONE_LEN    32
#define GICR_DFX_REGS_DFX_VLPI_ADD_SEARCH_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_WEIGHT_THR_LEN        8
#define GICR_DFX_REGS_DFX_WEIGHT_THR_OFFSET     4
#define GICR_DFX_REGS_DFX_CACHE_ALF0_THR_LEN    4
#define GICR_DFX_REGS_DFX_CACHE_ALF0_THR_OFFSET 0

#define GICR_DFX_REGS_DFX_MON_AWADDR_LEN    16
#define GICR_DFX_REGS_DFX_MON_AWADDR_OFFSET 16
#define GICR_DFX_REGS_DFX_MON_ARADDR_LEN    16
#define GICR_DFX_REGS_DFX_MON_ARADDR_OFFSET 0

#define GICR_DFX_REGS_DFX_MON_PTADDR_LEN    16
#define GICR_DFX_REGS_DFX_MON_PTADDR_OFFSET 0

#define GICR_DFX_REGS_DFX_MON_WDATA_LEN    32
#define GICR_DFX_REGS_DFX_MON_WDATA_OFFSET 0

#define GICR_DFX_REGS_DFX_MON_RDATA_LEN    32
#define GICR_DFX_REGS_DFX_MON_RDATA_OFFSET 0

#define GICR_DFX_REGS_DFX_PT_BYTE_LEN        8
#define GICR_DFX_REGS_DFX_PT_BYTE_OFFSET     1
#define GICR_DFX_REGS_DFX_PT_BYTE_ERR_LEN    1
#define GICR_DFX_REGS_DFX_PT_BYTE_ERR_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_FSM_CONFIT_LEN    1
#define GICR_DFX_REGS_DFX_LPI_FSM_CONFIT_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CFG_LEN    8
#define GICR_DFX_REGS_DFX_LPI_CFG_OFFSET 1
#define GICR_DFX_REGS_DFX_LPI_PT_LEN     1
#define GICR_DFX_REGS_DFX_LPI_PT_OFFSET  0

#define GICR_DFX_REGS_DFX_MOV_REQ_LEN    1
#define GICR_DFX_REGS_DFX_MOV_REQ_OFFSET 16
#define GICR_DFX_REGS_DFX_MOV_ID_LEN     16
#define GICR_DFX_REGS_DFX_MOV_ID_OFFSET  0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_SET_DONE_LEN    16
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_SET_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_CLR_DONE_LEN    16
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_CLR_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_INV_DONE_LEN    16
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_INV_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOV_DONE_LEN    16
#define GICR_DFX_REGS_DFX_LPI_CMD_LPI_MOV_DONE_OFFSET 0

#define GICR_DFX_REGS_DFX_LPI_ID_CNT_LEN    16
#define GICR_DFX_REGS_DFX_LPI_ID_CNT_OFFSET 0

#define GICR_DFX_REGS_DFX_GICR_IRQRX_CNT_LEN     16
#define GICR_DFX_REGS_DFX_GICR_IRQRX_CNT_OFFSET  16
#define GICR_DFX_REGS_DFX_GICR_IRQSET_CNT_LEN    16
#define GICR_DFX_REGS_DFX_GICR_IRQSET_CNT_OFFSET 0

#define GICR_DFX_REGS_DFX_GICR_IRQACTIVE_CNT_LEN      16
#define GICR_DFX_REGS_DFX_GICR_IRQACTIVE_CNT_OFFSET   16
#define GICR_DFX_REGS_DFX_GICR_IRQDEACTIVE_CNT_LEN    16
#define GICR_DFX_REGS_DFX_GICR_IRQDEACTIVE_CNT_OFFSET 0

#define GICR_DFX_REGS_DFX_GICR_IRQCLR_CNT_LEN        16
#define GICR_DFX_REGS_DFX_GICR_IRQCLR_CNT_OFFSET     16
#define GICR_DFX_REGS_DFX_GICR_IRQRELEASE_CNT_LEN    16
#define GICR_DFX_REGS_DFX_GICR_IRQRELEASE_CNT_OFFSET 0

#define GICR_DFX_REGS_DFX_GICR_IRQMERGE_CNT_LEN       16
#define GICR_DFX_REGS_DFX_GICR_IRQMERGE_CNT_OFFSET    16
#define GICR_DFX_REGS_DFX_GICR_IRQCORSSDIE_CNT_LEN    16
#define GICR_DFX_REGS_DFX_GICR_IRQCORSSDIE_CNT_OFFSET 0

#define GICR_DFX_REGS_DFX_RAS_NFE3_LEN    1
#define GICR_DFX_REGS_DFX_RAS_NFE3_OFFSET 4
#define GICR_DFX_REGS_DFX_RAS_NFE2_LEN    1
#define GICR_DFX_REGS_DFX_RAS_NFE2_OFFSET 3
#define GICR_DFX_REGS_DFX_RAS_NFE1_LEN    1
#define GICR_DFX_REGS_DFX_RAS_NFE1_OFFSET 2
#define GICR_DFX_REGS_DFX_RAS_NFE0_LEN    1
#define GICR_DFX_REGS_DFX_RAS_NFE0_OFFSET 1
#define GICR_DFX_REGS_DFX_SERR_LEN        1
#define GICR_DFX_REGS_DFX_SERR_OFFSET     0

#endif // __GICR_DFX_REGS_REG_OFFSET_FIELD_H__
